1. Field of the Invention
The present invention relates to a digital-to-analog converter, and more particularly to a resistor string digital-to-analog converter.
2. Description of Related Art
In recent years, it is demanded that digital-to-analog converters not only have a resolution higher than 10 bits but also achieve high accuracy and low cost.
Among others, high order/low order dividing resistor string digital-to-analog converters and interpolating amplifier resistor string digital-to-analog converters achieve high resolution and area reduction.
FIG. 10 shows an example configuration of a resistor string digital-to-analog converter that is related to the present invention. The resistor string digital-to-analog converter 5 shown in FIG. 10 includes a high-order resistor string 10, which includes a plurality of unit resistors 101 and a plurality of voltage acquisition points 102, first high-order switches 51x, 51y, a high-order decoder 52, a low-order decoder 53, a digital-to-analog converter for two lowest-order bits 15, second high-order switches 54x, 54y, 55x, 55y, and a buffer 18.
By way of example, it is assumed that the resistor string digital-to-analog converter 5 shown in FIG. 10 handles a 10-bit digital input signal 20, which has eight high-order bits and two low-order bits. The resistor string digital-to-analog converter 5 will now be described with reference to FIG. 10. First of all, the eight high-order bit data of the digital input signal 20 is input into the high-order decoder 52, whereas the two low-order bit data is input into the low-order decoder 53. When a value of the digital input signal 20 ranges from 4n to 4n+3, the high-order decoder 52 outputs a first high-order control signal 521, which turns on the first high-order switches 51x, 51y coupled to the nth and (n+1)th voltage acquisition points 102, for the purpose of outputting a pair of analog voltages from the nth and (n+1)th voltage acquisition points 102 from the low-order end of the high-order resistor string 10.
Next, the high-order decoder 52 outputs a second high-order control signal 522 for the purpose of controlling the second high-order switches 54x, 54y, 55x, 55y in accordance with the digital input signal 20. In accordance with the value of the digital input signal 20, the high-order decoder 52 recognizes the magnitude relationship between voltages applied to the high-order switches 51x, 51y. Next, the higher one of the pair of analog voltages is applied to the high-order end of a low-order resistor string 150, whereas the lower analog voltage is applied to the low-order end. A low-potential signal line VL and a high-potential signal line VH each have the buffer 18 in order to decrease the impedance.
The digital-to-analog converter for two lowest-order bits 15 generates four analog voltages, which are obtained by dividing an analog voltage present between the high-potential signal line VH and low-potential signal line VL. In accordance with the result of decoding of low-order 2-bit data, the low-order decoder 53 then turns on one of a plurality of low-order switches 151. Consequently, one of the four divided analog voltages is output as an analog output signal 30 corresponding to the digital input signal 20.
Meanwhile, a two-stage digital-to-analog converter disclosed in Japanese Unexamined Patent Publication No. 2001-44837 has a high-order conversion circuit and a low-order conversion circuit, which both include a plurality of series-coupled unit resistors and a plurality of switching elements coupled to coupling points of the unit resistors.